This invention relates to electrical circuits and more particularly to digital logic circuits. Even more particularly, the invention relates to a circuit for synchronizing data transfer between two data busses that are being clocked asynchronously.
In digital electronic systems, data is often transferred over a data bus wherein the data is sent in parallel signals and the transfer is synchronized with a clock signal. Such systems may have more than one data bus, and the busses are usually not synchronized to each other. That is, they run from different clocks, which causes them to be asynchronous with respect to each other. As well as being asynchronous, they also typically run at different speeds. When data must be transferred from one bus to another, the bus clock signals must be synchronized in some manner. This has been done conventionally by detecting a clock rising edge on the sending bus, then enabling the next rising edge on the receiving bus to latch the data onto the receiving bus.
In order to successfully transfer data on a bus, the data must be placed on the bus and allowed to stabilize before the rising edge of the clock signal transfers it to its destination. This stabilization time is called setup time. In prior art circuits, the performance of transfers between two busses is slow because data is not enabled onto the receiving bus until after the rising edge of the clock from the sending bus. Thus a second setup time is required on the receiving bus, and this setup time always occurs after the sending bus setup and rising edge of the sending clock.
Also, in prior art synchronization circuits, if the minimum pulse width of the sending bus clock is less than the period of the receiving clock, a rising edge of the sending clock may be missed, and the transfer will not occur until a subsequent cycle, further delaying the transfer or the system may fail to work.
Prior art circuits use the same design regardless of the speeds of the two busses, thus the delay in transferring data varies depending on the relative speed. That is, these circuits lack the ability to adjust to the two frequencies, to optimize, the data transfer. Sometimes this causes the prior art circuits to fail.
It is thus apparent that there is a need in the art for an improved method or apparatus which improves performance of data transfers between two data busses by allowing data transfer to occur during the setup time of the sending bus. There is a further need in the art for such a synchronization circuit that will detect sending bus clock pulses that occur between the edges of the receiving clock, and there is a still further need in the art for a synchronizer circuit that can be adjusted to optimize the data transfer, based on the speeds of the two busses.